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| HIP6521 TM Data Sheet August 2000 File Number 4837.1 PWM and Triple Linear Power Controller The HIP6521 provides the power control and protection for four output voltages in high-performance microprocessor and computer applications. The IC integrates a voltagemode PWM controller and three linear controllers, as well as monitoring and protection functions into a 16-lead SOIC package. The PWM controller is intended to regulate the microprocessor memory core voltage with a synchronousrectified buck converter. The linear controllers are intended to regulate the computer system's AGP 1.5V bus power, the 2.5V clock power, and the 1.8V power for the North/South Bridge core voltage and/or cache memory circuits. Both the switching regulator and linear voltage references provide 2% of static regulation over line, load, and temperature ranges. All outputs are user-adjustable by means of an external resistor divider. All linear controllers employ bipolar NPNs for the pass transistors. The HIP6521 monitors all the output voltages. The PWM controller's adjustable overcurrent function monitors the output current by using the voltage drop across the upper MOSFET's rDS(ON). The linear regulator outputs are monitored via the FB pins for undervoltage events. Features * Provides 4 Regulated Voltages - Memory Core, AGP, Clock, and Memory Controller Hub Power * ACPI Compatible * Drives Bipolar Linear Pass Transistors * Externally Resistor-Adjustable Outputs * Simple Single-Loop Control Design - Voltage-Mode PWM Control * Fast PWM Converter Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Ratio * Excellent Output Voltage Regulation - All Outputs: 2% Over Temperature * Overcurrent Fault Monitors - Switching Regulator Does Not Require Extra Current Sensing Element, Uses MOSFET's rDS(ON) * Small Converter Size - 300kHz Constant Frequency Operation - Small External Component Count Ordering Information PART NUMBER TEMP. RANGE (oC) HIP6521CB HIP6521EVAL1 0 to 70 Evaluation Board PACKAGE 16 Ld SOIC PKG. NO. M16.15 Related Literature * Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" Pinout Applications * Motherboard Power Regulation for Computers DRIVE2 1 FB2 2 FB 3 COMP 4 GND 5 PHASE 6 BOOT 7 UGATE 8 HIP6521 (SOIC) TOP VIEW 16 FB3 15 DRIVE3 14 FB4 13 DRIVE4 12 OCSET 11 VCC 10 LGATE 9 PGND 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000 Block Diagram FB3 OCSET VCC VCC EA4 DRIVE4 + x 0.70 - + 0.8V FB4 INHIBIT/SOFT-START DRIVE2 + DRIVE1 UGATE ++ BOOT EA2 FB2 + GND OSCILLATOR SYNC DRIVE - + + - - 2 EA3 DRIVE3 + POWER-ON RESET (POR) 40A - UV3 - UV4 HIP6521 SOFTSTART AND FAULT LOGIC OCC -- PHASE UV2 + - + PWM EA1 - GATE CONTROL COMP1 VCC LGATE PGND FB COMP HIP6521 Simplified Power System Diagram +5VSB (+5VDUAL) +5VDUAL +3.3VIN PWM CONTROLLER Q2 Q1 VOUT1 Q3 VOUT2 + LINEAR CONTROLLER + HIP6521 LINEAR CONTROLLER LINEAR CONTROLLER + VOUT3 Q4 + Q5 VOUT4 Typical Application +5VSB +5VDUAL LIN CIN + VCC +3.3VIN DRIVE2 FB2 Rs2 + COUT2 Rp2 UGATE PHASE Q1 LOUT1 BOOT OCSET CBOOT VOUT1 2.5V VOUT2 2.5V Q3 LGATE +3.3VDUAL Q4 DRIVE3 FB3 + Rs3 Rp3 COMP PGND Q2 COUT1 CR1 + HIP6521 VOUT3 1.8V FB Rs1 COUT3 VOUT4 1.5V + COUT4 Q5 DRIVE4 FB4 Rs4 Rp4 GND Rp1 3 HIP6521 Absolute Maximum Ratings UGATE, BOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V VCC, PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V DRIVE, LGATE, all other pins . . . . . . . . GND - 0.3V to VCC + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD Thermal Information Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Supply Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 10% Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 125oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications PARAMETER VCC SUPPLY CURRENT Nominal Supply Current POWER-ON RESET Rising VCC Threshold Falling VCC Threshold Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams, and Typical Application Schematic SYMBOL TEST CONDITIONS MIN TYP MAX UNITS ICC UGATE, LGATE, DRIVE2, DRIVE3, and DRIVE4 Open - 5 - mA 4.25 3.75 - 4.5 4.0 V V OSCILLATOR AND SOFT-START Free Running Frequency Ramp Amplitude Soft-Start Interval REFERENCE VOLTAGE Reference Voltage (All Regulators) All Outputs Voltage Regulation LINEAR REGULATORS (OUT2, OUT3, AND OUT4) Output Drive Current (All Linears) Undervoltage Level (VFB/VREF) VUV VCC > 4.5V 100 120 70 mA % VREF -2.0 0.800 +2.0 V % FOSC VOSC TSS 275 6.25 300 1.5 6.83 325 7.40 kHz VP-P ms SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate PWM CONTROLLER GATE DRIVERS UGATE Source UGATE Sink LGATE Source LGATE Sink PROTECTION OCSET Current Source IOCSET 34 40 46 A IUGATE IUGATE ILGATE ILGATE VCC = 5V, VUGATE = 2.5V VUGATE-PHASE = 2.5V VCC = 5V, VLGATE = 2.5V VLGATE = 2.5V -1 1 -1 2 A A A A GBWP SR COMP = 10pF 15 80 6 dB MHz V/s 4 HIP6521 Functional Pin Descriptions VCC (Pin 11) Provide a well decoupled 5V bias supply for the IC to this pin. This pin also provides the gate bias charge for the lower MOSFET controlled by the PWM section of the IC, as well as the base current drive for the linear regulators' external bipolar transistors. The voltage at this pin is monitored for Power-On Reset (POR) purposes. FB2, 3, 4 (Pins 2, 16, 14) Connect the output of the corresponding linear regulators to these pins through properly sized resistor dividers. The voltage at these pins is regulated to 0.8V. These pins are also monitored for undervoltage events. Quickly pulling and holding any of these pins above 1.25V (using diode-coupled logic devices) shuts off the respective regulators. Releasing these pins from the pull-up voltage initiates a soft-start sequence on the respective regulator. GND (Pin 5) Signal ground for the IC. All voltage levels are measured with respect to this pin. Description Operation The HIP6521 monitors and precisely controls 4 output voltage levels (Refer to Block and Simplified Power System Diagrams, and Typical Application Schematic). It is designed for microprocessor computer applications with 3.3V, and 5V (5VDUAL) bias input from an ATX power supply. The IC has a synchronous PWM controller and three linear controllers. The PWM controller (PWM) is designed to regulate the 2.5V memory voltage (VOUT1). The PWM controller drives 2 MOSFETs (Q1 and Q2) in a synchronous-rectified buck converter configuration and regulates the output voltage to a level programmed by a resistor divider. The linear controllers are designed to regulate three more of the computer system's voltages, typically the 1.5V AGP bus (VOUT4), the 2.5V clock voltage (VOUT2), and the 1.8V ICH/MCH core voltage (VOUT3). All linear controllers are designed to employ external NPN bipolar pass transistors. PGND (Pin 9) This is the power ground connection. Tie the synchronous PWM converter's lower MOSFET source to this pin. BOOT (Pin 7) Connect a suitable capacitor (0.47F recommended) from this pin to PHASE. This bootstrap capacitor supplies UGATE driver the energy necessary to turn and hold the upper MOSFET on. OCSET (Pin 12) Connect a resistor from this pin to the drain of the upper PWM MOSFET. This resistor, an internal 40A current source (typical), and the upper MOSFET's on-resistance set the converter overcurrent trip point. An overcurrent trip cycles the soft-start function. The voltage at this pin is monitored for power-on reset (POR) purposes and pulling this pin below 1.25V with an open drain/collector device will shutdown the switching controller. Initialization The HIP6521 automatically initializes upon receipt of input power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input bias supply voltage. The POR monitors the bias voltage at the VCC pin. The POR function initiates soft-start operation after the bias supply voltage exceeds its POR threshold. PHASE (Pin 6) Connect the PHASE pin to the PWM converter's upper MOSFET source. This pin is used to monitor the voltage drop across the upper MOSFET for overcurrent protection. UGATE (Pin 8) Connect UGATE pin to the PWM converter's upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. Soft-Start The POR function initiates the soft-start sequence. The PWM error amplifier reference input is clamped to a level proportional to the soft-start voltage. As the soft-start voltage slews up, the PWM comparator generates PHASE pulses of increasing width that charge the output capacitor(s). Similarly, all linear regulators' reference inputs are clamped to a voltage proportional to the soft-start voltage. The rampup of the internal soft-start function provides a controlled output voltage rise. Figure 1 shows the soft-start sequence for the typical application. At T0 the +5VSB bias voltage starts to ramp up (closely followed by the +5VDUAL voltage) crossing the 4.5V POR threshold at time T1. On the PWM section, the oscillator's triangular waveform is compared to the clamped error amplifier LGATE (Pin 10) Connect LGATE to the PWM converter's lower MOSFET gate. This pin provides the gate drive for the lower MOSFET. COMP and FB (Pins 4, 3) COMP and FB are the available external pins of the PWM converter error amplifier. The FB pin is the inverting input of the error amplifier. Similarly, the COMP pin is the error amplifier output. These pins are used to compensate the voltage-mode control feedback loop of the synchronous PWM converter. DRIVE2, 3, 4 (Pins 1, 15, 13) Connect these pins to the base terminals of external bipolar NPN transistors. These pins provide the base current drive for the regulator pass transistors. 5 HIP6521 output voltage. As the internal soft-start voltage increases, the pulse-width on the PHASE pin increases to reach its steadystate duty cycle at time T2. At time T3, the 3.3V input supply starts ramping up; as a result, VOUT2 and VOUT4 start ramping up on the second attempt (approximately 3.25 SS cycles wait), at time T4. During the interval between T4 and T5, the linear controller error amplifiers' references ramp to the final value bringing all outputs within regulation limits. overcurrent event, resulting in an UV condition. Similarly, after three soft-start periods, the fourth cycle initiates a ramp-up of this linear output at time T3. One soft-start period after T3, the linear output is within regulation limits. UV glitches less than 1s (typically) in duration are ignored. VOUT1 (2.5V) VOUT3 (1.8V) VOUT4 (1.5V) +5VSB +5VDUAL 0V +3.3VDUAL (0.5V/DIV.) UV MONITORING +3.3VIN VOUT2 (2.5V) ACTIVE 0V (1V/DIV) VOUT1 (2.5V) VOUT3 (1.8V) T0 VOUT4 (1.5V) T1 VOUT2 (2.5V) SOFT-START FUNCTION INACTIVE TIME T2 T3 T4 FIGURE 2. OVERCURRENT/UNDERVOLTAGE PROTECTION RESPONSE 0V (0.5V/DIV) T0 T1 T2 T3 TIME T4 T5 FIGURE 1. SOFT-START INTERVAL Overcurrent Protection All outputs are protected against excessive overcurrents. The PWM controller uses the upper MOSFET's on-resistance, rDS(ON) to monitor the current for protection against shorted output. All linear controllers monitor their respective FB pins for undervoltage events to protect against excessive currents. A sustained overload (undervoltage on linears or overcurrent on the PWM) on any output results in an independent shutdown of the respective output, followed by subsequent individual re-start attempts performed at an interval equivalent to 3 soft-start intervals. Figure 2 describes the protection feature. At time T0, an overcurrent event sensed across the switching regulator's upper MOSFET (rDS(ON) sensing) triggers a shutdown of the VOUT1 output. As a result, its internal soft-start initiates a number of soft-start cycles. After a three-cycle wait, the fourth soft-start initiates a ramp-up attempt of the failed output, at time T2, bringing the output in regulation at time T4. To exemplify an UV event on one of the linears, at time T1, the clock regulator (VOUT2) is also subjected to an 6 As overcurrent protection is performed on the synchronous switcher regulator on a cycle-by-cycle basis, OC monitoring is active as long as the regulator is operational. Since the overcurrent protection on the linear regulators is performed through undervoltage monitoring at the feedback pins (FB2, FB3, and FB4), this feature is activated approximately 25% into the soft-start interval (see Figure 2). A resistor (ROCSET) programs the overcurrent trip level for the PWM converter. As shown in Figure 3, the internal 40A current sink (IOCSET) develops a voltage across ROCSET (VSET) that is referenced to VIN . The DRIVE signal enables the overcurrent comparator (OCC). When the voltage across the upper MOSFET (VDS(ON)) exceeds VSET, the overcurrent comparator trips to set the overcurrent latch. Both VSET and VDS(ON) are referenced to VIN and a small capacitor across ROCSET helps VOCSET track the variations of VIN due to MOSFET switching. The overcurrent function will trip at a peak inductor current (IPEAK) determined by: I OCSET x R OCSET I PEAK = --------------------------------------------------r DS ( ON ) The OC trip point varies with MOSFET's rDS(ON) temperature variations. To avoid overcurrent tripping in the normal operating load range, determine the ROCSET resistor from the equation above with: HIP6521 1. The maximum rDS(ON) at the highest junction temperature. 2. The minimum IOCSET from the specification table. 3. Determine IPEAK for IPEAK > IOUT(MAX) + (I)/2, where I is the output inductor ripple current. OVERCURRENT TRIP: V DS > V SET VIN = +5V regulators have to meet the following criteria: their value while in a parallel connection has to be less than 5k, or otherwise said, the following relationship has to be met: RS x RP --------------------- < 5k RS + RP i D x r DS ( ON ) > I OCSET x R OCSET OCSET IOCSET 40A VCC DRIVE OC OCC PWM GATE CONTROL V PHASE = V IN - V DS V OCSET = V IN - V SET + UGATE PHASE + VDS(ON) ROCSET iD VSET + There may be a second restriction on the size of the resistors used to set the linear regulators' output voltage based on ACPI functionality. Read the `ACPI Implementation' section under `Application Guidelines' to see if this additional constraint concerns your application. To ensure the parallel combination of the feedback resistors equals a certain chosen value, RFB, use the following equations: V OUT R S = --------------- x R FB V FB R S x V FB R P = -------------------------------- , where V OUT - V FB - FIGURE 3. OVERCURRENT DETECTION VOUT - the desired output voltage, For an equation for the ripple current see the section under component guidelines titled `Output Inductor Selection'. VFB - feedback (reference) voltage, 0.8V. Output Voltage Selection The output voltage of the PWM converter can be resistorprogrammed to any level between VIN and 0.8V. However, since the value of RS1 is affecting the values of the rest of the compensation components, it is advisable its value is kept between 2k and 5k. 3.3VIN DRIVE3 FB3 + RS3 RP3 Application Guidelines Soft-Start Interval The soft-start function controls the output voltages rate of rise to limit the current surge at start-up. The soft-start function is integrated on the chip and the soft-start interval is thus fixed. Layout Considerations MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. Careful component layout and printed circuit design minimizes the voltage spikes in the converter. Consider, as an example, the turnoff transition of the upper PWM MOSFET. Prior to turn-off, the upper MOSFET was carrying the full load current. During the turn-off, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET or Schottky diode. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. See the Application Note AN9908 for evaluation board drawings of the component placement and printed circuit board. There are two sets of critical components in a DC-DC converter using a HIP6521 controller. The switching power components are the most critical because they switch large amounts of energy, and as such, they tend to generate Q4 VOUT3 COUT3 HIP6521 Q5 VOUT4 + RS4 RP4 DRIVE4 FB4 COUT4 R S V OUT = 0.8 x 1 + ------- R P FIGURE 4. ADJUSTING THE OUTPUT VOLTAGE OF ANY OF THE FOUR REGULATORS (OUTPUTS 3 AND 4 PICTURED) All linear regulators' output voltages are set by means of external resistor dividers as shown in Figure 4. The two resistors used to set the voltage on each of the three linear 7 HIP6521 equally large amounts of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bypass current. The power components and the controller IC should be placed first. Locate the input capacitors, especially the highfrequency ceramic decoupling capacitors, close to the power switches. Locate the output inductor and output capacitors between the MOSFETs and the load. Locate the PWM controller close to the MOSFETs. +5VIN LIN + CIN surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal wiring. The wiring traces from the control IC to the MOSFET gate and source should be sized to carry 2A peak currents. PWM Controller Feedback Compensation The PWM controller uses voltage-mode control for output regulation. This section highlights the design consideration for a PWM voltage-mode controller. Apply the methods and considerations only to the PWM controller. Figure 6 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level, 0.8V. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). VIN OSC PWM COMP DRIVER1 LO SYNC DRIVER PHASE CO + +12V CVCC VCC GND OCSET COCSET ROCSET VOUT2 + UGATE PHASE Q1 LOUT VOUT1 LOAD + LOAD COUT2 Q3 DRIVE2 LGATE Q2 COUT1 CR1 VOUT3 + COUT3 Q4 HIP6521 DRIVE3 DRIVE4 PGND Q5 + COUT4 VOUT4 VOUT VOSC LOAD - + LOAD ESR (PARASITIC) ZFB +3.3VIN VE/A KEY ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT OR POWER PLANE LAYER VIA CONNECTION TO GROUND PLANE + ERROR AMP 0.8V ZIN DETAILED COMPENSATION COMPONENTS C2 C1 R2 ZFB ZIN C3 RS1 R3 VOUT FIGURE 5. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS The critical small signal components include the bypass capacitor for VCC and the feedback resistors. Locate these components close to their connecting pins on the control IC. A multi-layer printed circuit board is recommended. Figure 5 shows the connections of the critical components in the converter. Note that the capacitors CIN and COUT each represent numerous physical capacitors. Dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the PHASE nodes, but do not unnecessarily oversize these particular islands. Since the PHASE nodes are subjected to very high dV/dt voltages, the stray capacitor formed between these islands and the COMP + FB RP1 0.8V HIP6521 FIGURE 6. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN The modulator transfer function is the small-signal transfer function of VOUT/VE/A . This function is dominated by a DC Gain, given by VIN/VOSC , and shaped by the output filter, with a double pole break frequency at FLC and a zero at FESR . 8 HIP6521 Modulator Break Frequency Equations 1 F LC = --------------------------------------2 x L O x C O 1 F ESR = ---------------------------------------2 x ESR x C O 100 80 60 GAIN (dB) 40 20 0 -20 -40 -60 R2 20 log ------------ R S1 MODULATOR GAIN FLC 1K FESR 10K 100K 1M CLOSED LOOP GAIN FZ1 FZ2 FP1 FP2 OPEN LOOP ERROR AMP GAIN V IN 20 log ----------- V PP The compensation network consists of the error amplifier (internal to the HIP6521) and the impedance networks ZIN and ZFB . The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network's poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 6. Use these guidelines for locating the poles and zeros of the compensation network: 1. Pick Gain (R2/R1) for desired converter bandwidth 2. Place 1ST Zero Below Filter's Double Pole (~75% FLC) 3. Place 2ND Zero at Filter's Double Pole 4. Place 1ST Pole at the ESR Zero 5. Place 2ND Pole at Half the Switching Frequency 6. Check Gain against Error Amplifier's Open-Loop Gain 7. Estimate Phase Margin - Repeat if Necessary COMPENSATION GAIN 10 100 10M FREQUENCY (Hz) FIGURE 7. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN ACPI Implementation The three linear controllers included within the HIP6521 can independently be shut down, in order to accommodate Advanced Configuration and Power Interface (ACPI) power management features. To shut down any of the linears, one needs to pull and keep high the respective FB pin above a typical threshold of 1.25V. One way to achieve this task is by using a logic gate coupled through a small-signal diode. The diode should be placed as close to the FB pin as possible to minimize stray capacitance to this pin. Upon turn-off of the pull-up device, the respective output undergoes a soft-start cycle, bringing the output within regulation limits. On the regulators implementing this feature, the parallel combination of the feedback resistors has to be sufficiently high to allow ease of driving from the external device. Considering the other restriction applying to the upper range of this resistor combination (see `Output Voltage Selection' paragraph), it is recommended the values of the feedback resistors on an ACPI-enabled linear regulator output meet the following constraint: RS x RP 2k < --------------------- < 5k RS + RP Compensation Break Frequency Equations 1 F Z1 = ----------------------------------2 x R 2 x C1 1 F Z2 = --------------------------------------------------------2 x ( R S1 + R3 ) x C3 1 F P1 = -----------------------------------------------------C1 x C2 2 x R 2 x --------------------- C1 + C2 1 F P2 = ----------------------------------2 x R 3 x C3 Figure 7 shows an asymptotic plot of the DC-DC converter's gain vs. frequency. The actual Modulator Gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown in Figure 6. Using the above guidelines should yield a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 10 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. To turn off the switching regulator, use an open-drain or open-collector device capable of pulling the OCSET pin (with the attached ROCSET pull-up) below 1.25V. To minimize the possibility of OC trips at levels different than predicted, a COCSET capacitor with a value of an order of magnitude larger than the output capacitance of the pull-down device, has to be used in parallel with ROCSET (1nF recommended). Upon turn-off of the pull-down device, the switching regulator undergoes a soft-start cycle. Important If the collector voltage to a linear regulator pass transistor (Q3, Q4, or Q5) is lost, the respective regulator has to be 9 HIP6521 shut down by pulling high its FB pin (i.e., when an input power rail shuts down as a result of entering a sleep state, the affected regulator's FB pin has to be pulled high). This measure is necessary in order to avoid possible damage to the HIP6521 as a result of overheating. Overheating can occur in such situations due to sheer power dissipation inside the chip's output linear drivers. PWM Output Inductor Selection The PWM converter requires an output inductor. The output inductor is selected to meet the output voltage ripple requirements and sets the converter's response time to a load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations: V IN - V OUT V OUT I = ------------------------------- x --------------V IN FS x L V OUT = I x ESR Component Selection Guidelines Output Capacitor Selection The output capacitors for each output have unique requirements. In general, the output capacitors should be selected to meet the dynamic regulation requirements. Additionally, the PWM converters require an output capacitor to filter the current ripple. The load transient for the microprocessor core requires high quality capacitors to supply the high slew rate (di/dt) current demands. Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values increase the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the HIP6521 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time interval required to slew the inductor current from an initial current value to the post-transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: L O x I TRAN t RISE = ------------------------------V IN - V OUT L O x I TRAN t FALL = -----------------------------V OUT PWM Output Capacitors Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR determines the output ripple voltage and the initial voltage drop following a high slew-rate transient's edge. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Input Capacitor Selection The important parameters for the bulk input capacitors are the voltage rating and the RMS current rating. For reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 of the summation of the DC load current. Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use ceramic capacitance for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be Linear Output Capacitors The output capacitors for the linear regulators provide dynamic load current. The linear controllers use dominant pole compensation integrated into the error amplifier and are insensitive to output capacitor selection. Output capacitors should be selected for transient load regulation. 10 HIP6521 placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedances. For a through-hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. +5V OR LESS +5V VCC BOOT CBOOT UGATE PHASE VCC Q1 NOTE: VGS VCC -0.5V Q2 CR1 NOTE: VGS VCC + HIP6521 Transistors Selection/Considerations The HIP6521 requires 5 external transistors. Two N-channel MOSFETs are used in the synchronous-rectified buck topology of PWM converter. The clock, AGP and MCH/ICH linear controllers each drive an NPN bipolar transistor as a pass element. All these transistors should be selected based upon rDS(ON) , current gain, saturation voltages, gate/base supply requirements, and thermal management considerations. - LGATE PGND GND + FIGURE 8. MOSFET GATE BIAS PWM MOSFET Selection and Considerations In high-current PWM applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. These losses are distributed between the upper and lower MOSFETs according to duty factor (see the equations below). The conduction losses are the main component of power dissipation for the lower MOSFETs. Only the upper MOSFET has significant switching losses, since the lower device turns on and off into near zero voltage. The equations below assume linear voltage-current transitions and do not model power loss due to the reverserecovery of the lower MOSFET's body diode. The gatecharge losses are dissipated by the HIP6521 and don't heat the MOSFETs. However, large gate-charge increases the switching time, tSW which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. I O x r DS ( ON ) x V OUT I O x V IN x t SW x F S P UPPER = ----------------------------------------------------------- + ---------------------------------------------------V IN 2 I O x r DS ( ON ) x ( V IN - V OUT ) P LOWER = -------------------------------------------------------------------------------V IN 2 2 Rectifier CR1 is a clamp that catches the negative inductor swing during the dead time between the turn off of the lower MOSFET and the turn on of the upper MOSFET. The diode must be a Schottky type to prevent the lossy parasitic MOSFET body diode from conducting. It is acceptable to omit the diode and let the body diode of the lower MOSFET clamp the negative inductor swing, providing the body diode is fast enough to avoid excessive negative voltage swings at the PHASE pin. The diode's rated reverse breakdown voltage must be greater than the maximum input voltage. Linear Controllers Transistor Selection The main criteria for selection of transistors for the linear regulators is package selection for efficient removal of heat. The power dissipated in a linear regulator is: P LINEAR = I O x ( V IN - V OUT ) Select a package and heatsink that maintains the junction temperature below the rating with a the maximum expected ambient temperature. As bipolar NPN transistors have to be used with the linear controllers, insure the current gain at the given operating VCE is sufficiently large to provide the desired maximum output load current when the base is fed with the minimum driver output current. Given the reduced available gate bias voltage (5V) logiclevel or sub-logic-level transistors have to be used for both N-MOSFETs. Caution should be exercised with devices exhibiting very low VGS(ON) characteristics, as the low gate threshold could be conducive to some shoot-through (due to the Miller effect), in spite of the counteracting circuitry present aboard the HIP6521. 11 HIP6521 HIP6521 DC-DC Converter Application Circuit Figure 9 shows an application circuit of a power supply for a microprocessor computer system. The power supply provides the system memory voltage (VOUT1), the AGP bus voltage (VOUT4), the clock voltage (VOUT2), and the chip set core voltage (VOUT3) from +5VDUAL. For detailed information on the circuit, including a Bill-of-Materials and circuit board description, see Application Note AN9908. Also see Intersil's web page (www.intersil.com) or Intersil AnswerFAX (321-724-7800) Document No. 99908 for the latest information. L1 +5VDUAL 1.2H GND C1-3 + 3x1200F C4 1F C5 1000pF C6 1F VCC +3.3VIN Q3 FZT649 R2 12.7K C8 + 330F R3 5.90K 8 6 DRIVE2 FB2 1 2 UGATE PHASE 2.5H (2.5V) Q1,2 HUF76129D3S C9-12 + 4x1000F C7 0.47F L2 VOUT1 11 R1 12 7 OCSET BOOT 12K D1 MA732 VOUT2 (2.5V) +3.3VDUAL Q4 2SD1802 R4 + 9.09K C13 1000F DRIVE3 FB3 R5 7.15K 15 16 U1 HIP6521 10 9 LGATE PGND VOUT3 (1.8V) 3 FB R6 1.50K 4 Q5 2SD1802 DRIVE4 R9 7.50K + C16 1000F FB4 R10 8.45K 13 14 5 GND COMP C14 10pF VOUT4 (1.5V) C15 22nF R7 45.3K R8 698 To FB2 S3 To FB4 To OCSET S5 FIGURE 9. POWER SUPPLY APPLICATION CIRCUIT FOR A MICROPROCESSOR COMPUTER SYSTEM 12 HIP6521 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574 A1 B C D A1 0.10(0.004) C E e H h L N e B 0.25(0.010) M C AM BS 0.050 BSC 0.2284 0.0099 0.016 16 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 16 0o 6.20 0.50 1.27 NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369 13 This datasheet has been download from: www..com Datasheets for electronics components. |
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